The project aims to develop an Interference-Resilient VDE-SAT baseband demodulator integrated with Digital Signal Processing (DSP) solutions to mitigate Radio Frequency Interference (RFI). Its goal is to enhance Uplink (UL) demodulation performance in the presence of maritime and terrestrial interference, enabling uncoordinated satellite access schemes in VHF bands.
Key Benefits & Features
- Baseband Processing: RFI mitigation operates directly on raw IQ samples from the VHF receiver stages, making it ideal for small satellite platforms.
- Cascaded Architecture: RFI mitigation techniques are applied sequentially to maximize interference reduction while preserving the useful signal.
- Performance & KPI Tracking: Each demodulation chain provides Link ID payloads alongside key metrics (SNR, Doppler shift, PLR) to continuously assess system performance.
Technical Challenges
- On-Board Processing Constraints: Combining time and frequency domain techniques (such as Pulse or Frequency blanking), Interference Cancellation (IC), and Self-Interference Cancellation (SIC) requires significant computational power.
- Adaptive Solution: Unlike ground stations equipped with high-performance CPU/GPU servers, a small satellite’s onboard processor will execute a select subset of available mitigation techniques in real time.
On-Board System Architecture
- Front-End & Antenna: Directive antennas (Yagi or VHF array) paired with dynamic AGC to prevent signal saturation and enable digital beam/null steering.
- eRFI Module: Real-time processing of raw IQ samples across a 150 kHz bandwidth (3 channels of 50 kHz each).
- Parallel Demodulation: Parallel execution of 3 baseband demodulators handling up to 3 UL channels.
- MAI SIC Module: Dedicated module for Multiple Access Interference (MAI) cancellation, applied post-demodulation (tailored for Link ID20).
Roadmap & Current Status Development Phases (18 Months)
- Phase 1: Initial trade-off analysis and state-of-the-art survey.
- Phase 2: Simulation using MATLAB models (pulse/frequency blanking, notch filtering, IC, SIC).
- Phase 3: Software/hardware implementation (C++/HDL).
- Phase 4: Laboratory and live testing.
MARLIN: Maritime LEO Interference mitigation
ultima modifica: 2026-10-22T12:24:13+02:00
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